In the rapidly developing technology of imaging systems such as infrared detector focal plane arrays, sensitivity and performance of the imager may be dramatically enchanced by processing the video data generated by the imager. Well-known algorithms are available which enhance the performance of the imager, including algorithms to perform edge detection and local averaging. Unfortunately, such processing cannot be performed in real time in practical application. For example, a standard video format may comprise a video frame generated once every 1/60th of a second, each video frame comprising 256 rows by 256 columns of image pixels. A standard edge detection operator operates on a kernel comprising 3 rows by 3 columns of image pixels, the kernel being a window which must be moved about the entire frame each 1/60th of a second. In this example, a processor programmed to perform the algorithm must operate at a computation rate of approximately 35 million operations per second. This exceeds the computation rate of most programmable processors. Thus, a programmable processor cannot perform the edge detection algorithm in real time.
As used in this specification, the term processor refers to a device which performs computations upon data stored in memory in response to instructions also stored in memory. A programmable processor is that processor in which the instruction words stored in memory may be changed by the user so that the processor operates upon the data stored in memory according to the algorithm selected by the user.
In most laboratories investigating image processing, unprocessed video data is stored in a large computer memory to permit a processor to perform, for example, an edge detection algorithm on the video data at a leisurely pace. Such an arrangement is unacceptable when the imager is to be used, for example, in a guided vehicle in which the results of the edge detection algorithm must be available instantly to the vehicle guidance system to permit real time control.
In an attempt to solve the problem of real time image processing by substituting a plurality of processors which share each video frame among themselves, the communication time required for all the processors to time share the video data among themselves substantially offsets the advantage gained by increasing the number of processors. In an attempt to eliminate the time consumed by time sharing communication between processors, an arbitrator may be imposed which controls the distribution of the video data to each of the individual processors, thus eliminating the need for processor-to-processor time sharing communication. Unfortunately, the arbitrator itself imposes time delays required by the sorting operation performed by the arbitrator, thus offsetting the advantage gained by using a plurality of processors. Accordingly, the computation rate of available programmable processors remains a limitation on the video data rate at which real time image processing can be performed, a significant disadvantage.
Currently available real time image processors are hard-wired systems which, because they do not execute programmed instructions, can perform a sufficient number of operations per second which are comparable to or exceed the video data rate of most video systems. Such hard-wired processors are not programmable, a significant disadvantage when versatility is a system requirement. For example, there are several image enhancement algorithms which may be useful under different circumstances encountered by the video imager. It may be desirable to change instantly from a local averaging algorithm to an edge detection algorithm while viewing a particular scene. Such versatility vastly enhances the usefulness of the video imager and is not possible using a hard-wired processor. Thus, it has remained a goal in the art to perform real time programmable image enhancement processing on high speed video data formats.